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VHDL (5 cr)

Code: 5051158-3003

General information


Enrollment

02.07.2020 - 06.09.2020

Timing

07.09.2020 - 31.12.2020

Number of ECTS credits allocated

5 op

Mode of delivery

Contact teaching

Unit

Engineering and Business

Teaching languages

  • English

Seats

0 - 50

Degree programmes

  • Degree Programme in Information and Communication Technology
  • Degree Programme in Information and Communications Technology

Teachers

  • Jarno Tuominen

Teacher in charge

Jarno Tuominen

Groups

  • PTIVIS18S
    PTIVIS18S

Objective

After completing the course the student:
- can design and implement digital logic using VHDL language
- knows basic principles of FPGA functionality.

Content

- VHDL
- combinatorial logic
- sequential logic
- state machines
- FPGA

Materials

Will be informed at the beginning of the course

Teaching methods

Lectures
Exercises
Self study
Project work (to be confirmed)
Written (short) exam

Exam schedules

Exam 1: W50
Exam 2: TBD
Exam 3: TBD

Completion alternatives

None

Student workload

Contact teaching / lectures 12*1h (12h)
Contact teaching / lab work 12*3h (36h)
Project work (TBD)
Self studying / independent work (90h - Project work)
Exam (2h)

Total: 140h

Content scheduling

VHDL programming
Course duration 7.9.2020 - 7.12.2020
Topics:
- VHDL
- combinatorial logic
- sequential logic
- state machines
- FPGA
After completing the course the student:
- can design and implement digital logic using VHDL language

Further information

Basic skills in programming (any language) is mandatory
Basic skills in electronics is highly recommended
This is a laboratory course
The tools used in this course require a lot of hard disk space on your laptop (>10GB)
Support is given primarily for windows-environment, Linux can be used as well (limited support). No support for Mac users, tools must be run in virtual machine, which is very likely to cause big problems. Thus, Mac highly not recommended.

Evaluation scale

H-5

Assessment methods and criteria

Exam 25%
Lab exercises 75%
Project work TBD%

Assessment criteria, fail (0)

Less than 66% of lab exercises completed
OR
Less than 10 points in exam
OR (TBD)
Project work not submitted

Assessment criteria, satisfactory (1-2)

grade 1: 66% of lab exercises completed, 50% of max points in exam

Assessment criteria, good (3-4)

To be defined

Assessment criteria, excellent (5)

To be defined

Qualifications

Introduction to Electronics and Transmission