•   VHDL 5051158-3005 30.08.2021-31.12.2021  5 credits  (ICTMODembeddedSem, ...) +-
    Competence objectives of study unit
    After completing the course the student:
    - can design and implement digital logic using VHDL language
    - knows basic principles of FPGA functionality.
    Prerequisites
    Introduction to Electronics and Transmission
    Content of study unit
    - VHDL

    - combinatorial logic

    - sequential logic

    - state machines

    - FPGA

    Teacher(s) in charge

    Ville Huhtinen, Jarno Tuominen, Juho Koskinen

    Learning material

    Will be informed at the beginning of the course

    Learning methods

    Lectures
    Exercises
    Self study
    Project work (to be confirmed)
    Written (short) exam

    Objects, timing and methods of assessment

    Exam 25%
    Lab exercises 75%
    Project work TBD%

    Teaching language

    Finnish

    Timing

    30.08.2021 - 31.12.2021

    Enrollment date range

    01.08.2021 - 06.09.2021

    Group(s)
    • ICTMODembeddedSem
    • PTIVIS19S
    Seats

    0 - 60

    Responsible unit

    Engineering and Business

    Additional information

    Basic skills in programming (any language) is mandatory
    Basic skills in electronics is highly recommended
    This is a laboratory course
    The tools used in this course require a lot of hard disk space on your laptop (>10GB)
    Support is given primarily for windows-environment, Linux can be used as well (limited support). No support for Mac users, tools must be run in virtual machine, which is very likely to cause big problems. Thus, Mac highly not recommended.

    Degree Programme(s)

    Degree Programme in Information and Communication Technology, Degree Programme in Information and Communications Technology

    Assessment scale

    H-5

    Alternative methods of attainment for implementation

    None

    Exam dates and retake possibilities

    Exam 1: W49
    Exam 2: TBD
    Exam 3: TBD

    Student's schedule and workload

    Contact teaching / lectures 12*1h (12h)
    Contact teaching / lab work 12*3h (36h)

    Self studying / independent work (90h)
    Exam (2h)

    Total: 140h

    Content scheduling

    VHDL programming
    Course duration 30.8.2021 - 6.12.2021
    Topics:
    - VHDL
    - combinatorial logic
    - sequential logic
    - state machines
    - FPGA
    After completing the course the student:
    - can design and implement digital logic using VHDL language
    - knows principles of FPGA technology and related tools

    Assessment criteria
    Failed (0)

    Less than 66% of lab exercises completed
    OR
    Less than 10 points in exam
    OR (TBD)
    Project work not submitted

    Assessment criteria – satisfactory (1-2)

    grade 1: 66% of lab exercises completed, 50% of max points in exam

    Assessment criteria – good (3-4)

    To be defined

    Assessment criteria – excellent (5)

    To be defined