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Digital systems design (5 cr)

Code: TE00DJ62-3001

General information


Enrollment
02.08.2025 - 07.09.2025
Registration for introductions has not started yet. Registration starts :startDate
Timing
01.09.2025 - 21.12.2025
The implementation has not yet started.
Number of ECTS credits allocated
5 cr
Local portion
5 cr
Mode of delivery
Contact learning
Unit
Engineering and Business
Campus
Kupittaa Campus
Teaching languages
English
Seats
10 - 60
Degree programmes
Degree Programme in Information and Communications Technology
Degree Programme in Information and Communication Technology
Teachers
Jarno Tuominen
Teacher in charge
Jarno Tuominen
Scheduling groups
DigSys Lab group 1 (Size: 20 . Open UAS : 0.)
DigSys Lab group 2 (Size: 20 . Open UAS : 0.)
Groups
PTIVIS23S
Embedded Software and IoT
Vaihto2526embo
Embedded Software and IoT
Small groups
DigSys Lab group 1
DigSys Lab group 2
Course
TE00DJ62

Realization has 33 reservations. Total duration of reservations is 73 h 0 min.

Time Topic Location
Thu 04.09.2025 time 08:00 - 09:00
(1 h 0 min)
Digital systems design TE00DJ62-3001
ICT_C3027 Sulautettujen ohjelmistojen laboratorio/IT
Thu 04.09.2025 time 09:00 - 12:00
(3 h 0 min)
Digital systems design TE00DJ62-3001
ICT_C3027 Sulautettujen ohjelmistojen laboratorio/IT
Thu 04.09.2025 time 12:00 - 15:00
(3 h 0 min)
Digital systems design TE00DJ62-3001
ICT_C3027 Sulautettujen ohjelmistojen laboratorio/IT
Mon 08.09.2025 time 14:00 - 15:00
(1 h 0 min)
Digital systems design TE00DJ62-3001
ICT_C3027 Sulautettujen ohjelmistojen laboratorio/IT
Mon 08.09.2025 time 15:00 - 18:00
(3 h 0 min)
Digital systems design TE00DJ62-3001
ICT_C3027 Sulautettujen ohjelmistojen laboratorio/IT
Tue 09.09.2025 time 15:00 - 18:00
(3 h 0 min)
Digital systems design TE00DJ62-3001
ICT_C3027 Sulautettujen ohjelmistojen laboratorio/IT
Thu 18.09.2025 time 08:00 - 09:00
(1 h 0 min)
Digital systems design TE00DJ62-3001
ICT_C3027 Sulautettujen ohjelmistojen laboratorio/IT
Thu 18.09.2025 time 09:00 - 12:00
(3 h 0 min)
Digital systems design TE00DJ62-3001
ICT_C3027 Sulautettujen ohjelmistojen laboratorio/IT
Thu 18.09.2025 time 12:00 - 15:00
(3 h 0 min)
Digital systems design TE00DJ62-3001
ICT_C3027 Sulautettujen ohjelmistojen laboratorio/IT
Thu 25.09.2025 time 08:00 - 09:00
(1 h 0 min)
Digital systems design TE00DJ62-3001
ICT_C3027 Sulautettujen ohjelmistojen laboratorio/IT
Thu 25.09.2025 time 09:00 - 12:00
(3 h 0 min)
Digital systems design TE00DJ62-3001
ICT_C3027 Sulautettujen ohjelmistojen laboratorio/IT
Thu 25.09.2025 time 12:00 - 15:00
(3 h 0 min)
Digital systems design TE00DJ62-3001
ICT_C3027 Sulautettujen ohjelmistojen laboratorio/IT
Thu 02.10.2025 time 08:00 - 09:00
(1 h 0 min)
Digital systems design TE00DJ62-3001
ICT_C3027 Sulautettujen ohjelmistojen laboratorio/IT
Thu 02.10.2025 time 09:00 - 12:00
(3 h 0 min)
Digital systems design TE00DJ62-3001
ICT_C3027 Sulautettujen ohjelmistojen laboratorio/IT
Thu 02.10.2025 time 12:00 - 15:00
(3 h 0 min)
Digital systems design TE00DJ62-3001
ICT_C3027 Sulautettujen ohjelmistojen laboratorio/IT
Thu 09.10.2025 time 08:00 - 09:00
(1 h 0 min)
Digital systems design TE00DJ62-3001
ICT_C3027 Sulautettujen ohjelmistojen laboratorio/IT
Thu 09.10.2025 time 09:00 - 12:00
(3 h 0 min)
Digital systems design TE00DJ62-3001
ICT_C3027 Sulautettujen ohjelmistojen laboratorio/IT
Thu 09.10.2025 time 12:00 - 15:00
(3 h 0 min)
Digital systems design TE00DJ62-3001
ICT_C3027 Sulautettujen ohjelmistojen laboratorio/IT
Thu 23.10.2025 time 08:00 - 09:00
(1 h 0 min)
Digital systems design TE00DJ62-3001
ICT_C3027 Sulautettujen ohjelmistojen laboratorio/IT
Thu 23.10.2025 time 09:00 - 12:00
(3 h 0 min)
Digital systems design TE00DJ62-3001
ICT_C3027 Sulautettujen ohjelmistojen laboratorio/IT
Thu 23.10.2025 time 12:00 - 15:00
(3 h 0 min)
Digital systems design TE00DJ62-3001
ICT_C3027 Sulautettujen ohjelmistojen laboratorio/IT
Thu 30.10.2025 time 09:00 - 10:00
(1 h 0 min)
Digital systems design TE00DJ62-3001
ICT_C3027 Sulautettujen ohjelmistojen laboratorio/IT
Thu 30.10.2025 time 10:00 - 13:00
(3 h 0 min)
Digital systems design TE00DJ62-3001
ICT_C3027 Sulautettujen ohjelmistojen laboratorio/IT
Thu 30.10.2025 time 13:00 - 16:00
(3 h 0 min)
Digital systems design TE00DJ62-3001
ICT_C3027 Sulautettujen ohjelmistojen laboratorio/IT
Thu 06.11.2025 time 08:00 - 09:00
(1 h 0 min)
Digital systems design TE00DJ62-3001
ICT_C3027 Sulautettujen ohjelmistojen laboratorio/IT
Thu 06.11.2025 time 09:00 - 12:00
(3 h 0 min)
Digital systems design TE00DJ62-3001
ICT_C3027 Sulautettujen ohjelmistojen laboratorio/IT
Thu 06.11.2025 time 12:00 - 15:00
(3 h 0 min)
Digital systems design TE00DJ62-3001
ICT_C3027 Sulautettujen ohjelmistojen laboratorio/IT
Thu 13.11.2025 time 08:00 - 09:00
(1 h 0 min)
Digital systems design TE00DJ62-3001
ICT_C3027 Sulautettujen ohjelmistojen laboratorio/IT
Thu 13.11.2025 time 09:00 - 12:00
(3 h 0 min)
Digital systems design TE00DJ62-3001
ICT_C3027 Sulautettujen ohjelmistojen laboratorio/IT
Thu 13.11.2025 time 12:00 - 15:00
(3 h 0 min)
Digital systems design TE00DJ62-3001
ICT_C3027 Sulautettujen ohjelmistojen laboratorio/IT
Thu 20.11.2025 time 08:00 - 09:00
(1 h 0 min)
Digital systems design TE00DJ62-3001
ICT_C3027 Sulautettujen ohjelmistojen laboratorio/IT
Thu 27.11.2025 time 08:00 - 09:00
(1 h 0 min)
Digital systems design TE00DJ62-3001
ICT_C3027 Sulautettujen ohjelmistojen laboratorio/IT
Thu 04.12.2025 time 08:00 - 09:00
(1 h 0 min)
Digital systems design TE00DJ62-3001
ICT_C3027 Sulautettujen ohjelmistojen laboratorio/IT
Changes to reservations may be possible.

Evaluation scale

H-5

Content scheduling

VHDL/FPGA development
Course duration 9/2022 - 12/2022
Topics:
- VHDL
- combinatorial logic
- sequential logic
- state machines
- FPGA
After completing the course the student:
- can design and implement digital logic using VHDL language
- knows principles of FPGA technology and related tools
- understands the basics of computer architecture

Objective

After completing the course the student:
- can design and implement digital logic using VHDL language
- knows basic principles of FPGA functionality.

Content

- VHDL
- combinatorial logic
- sequential logic
- state machines
- FPGA

Materials

Will be informed at the beginning of the course

Teaching methods

Lectures
Exercises
Self study
Written (short) exam

Exam schedules

To be agreed during the course
Exam 1: TBD
Exam 2: TBD
Exam 3: TBD

Pedagogic approaches and sustainable development

Emphasis is on learning by doing, presence is mandatory due to special equipment.
No specific topics related to sustainability.

Completion alternatives

No alternative methods

Student workload

Lectures 10 x 1h
Lab Exercises 10 x 3h
Exam 1h (re-exams, 2 x 1h)
Self study 94h

Evaluation methods and criteria

Exam 25%
Lab exercises 75%

Failed (0)

Less than 66% of lab exercises completed
OR
Less than 50% of points in exam

Assessment criteria, satisfactory (1-2)

grade 1: 66% of lab exercises completed, 50% of max points in exam
Grades 1-5 are calculated linearly, assuming both conditions for passing the course are met.

Assessment criteria, good (3-4)

grade 1: 66% of lab exercises completed, 50% of max points in exam
Grades 1-5 are calculated linearly, assuming both conditions for passing the course are met.

Assessment criteria, excellent (5)

grade 1: 66% of lab exercises completed, 50% of max points in exam
Grades 1-5 are calculated linearly, assuming both conditions for passing the course are met.

Qualifications

Introduction to Electronics

Further information

Basic skills in programming (any language) is mandatory
Basic skills in electronics is highly recommended
This is a laboratory course
The tools used in this course require a lot of hard disk space on your laptop (>80GB)
Support is given primarily for Linux-environment, the tools are executes in virtual machine environment. No support for Mac users, tools must be run in virtual machine, which is very likely to cause big problems, especially for ARM-based laptops. Thus, Mac not recommended.

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