VHDL (5 cr)

Evaluation scale

H-5

Content scheduling

VHDL/FPGA development
Course duration 9/2022 - 12/2022
Topics:
- VHDL
- combinatorial logic
- sequential logic
- state machines
- FPGA
After completing the course the student:
- can design and implement digital logic using VHDL language
- knows principles of FPGA technology and related tools
- understands the basics of computer architecture

Objective

After completing the course the student:
- can design and implement digital logic using VHDL language
- knows basic principles of FPGA functionality.

Content

- VHDL
- combinatorial logic
- sequential logic
- state machines
- FPGA

Materials

Will be informed at the beginning of the course

Teaching methods

Lectures
Exercises
Self study
Project work (to be confirmed)
Written (short) exam

Exam schedules

Exam 1: W49
Exam 2: TBD
Exam 3: TBD

Completion alternatives

None

Student workload

Contact teaching / lectures 12*1h (12h)
Contact teaching / lab work 12*3h (36h)

Self studying / independent work (90h)
Exam (2h)

Total: 140h

Evaluation methods and criteria

Exam 25%
Lab exercises 75%
Project work TBD%

Failed (0)

Less than 66% of lab exercises completed
OR
Less than 10 points in exam
OR (TBD)
Project work not submitted

Assessment criteria, satisfactory (1-2)

grade 1: 66% of lab exercises completed, 50% of max points in exam

Assessment criteria, good (3-4)

To be defined

Assessment criteria, excellent (5)

To be defined

Qualifications

Introduction to Electronics and Transmission

Further information

Basic skills in programming (any language) is mandatory
Basic skills in electronics is highly recommended
This is a laboratory course
The tools used in this course require a lot of hard disk space on your laptop (>10GB)
Support is given primarily for windows-environment, Linux can be used as well (limited support). No support for Mac users, tools must be run in virtual machine, which is very likely to cause big problems. Thus, Mac highly not recommended.