Upcoming implementations:

•   VHDL 5051158-3008 31.08.2023-31.12.2023  5 credits  (ICTMODembeddedSem, ...) +-
  Teacher(s) in charge

  Jarno Tuominen

  Learning material

  Will be informed at the beginning of the course

  Learning methods

  Lectures
  Exercises
  Self study
  Written (short) exam

  Objects, timing and methods of assessment

  Exam 25%
  Lab exercises 75%
  Project work TBD%

  Teaching language

  English

  Timing

  31.08.2023 - 31.12.2023

  Enrollment date range

  01.08.2023 - 07.09.2023

  Group(s)

  • ICTMODembeddedSem
  • PTIVIS21S

  Seats

  20 - 40

  Responsible unit

  Engineering and Business

  Small group(s)

  • Group 1 (Size: 25.
  • Group 2 (Size: 25.

  Additional information

  Basic skills in programming (any language) is mandatory
  Basic skills in electronics is highly recommended
  This is a laboratory course
  The tools used in this course require a lot of hard disk space on your laptop (>10GB)
  Support is given primarily for windows-environment, Linux can be used as well (limited support). No support for Mac users, tools must be run in virtual machine, which is very likely to cause big problems. Thus, Mac highly not recommended.

  Degree Programme(s)

  Degree Programme in Information and Communication Technology, Degree Programme in Information and Communications Technology

  Campus

  Kupittaa Campus

  RDI share

  0.00 credits

  Share of online studies

  0.00 credits

  Assessment scale

  H-5

  Alternative methods of attainment for implementation

  None

  Exam dates and retake possibilities

  Exam 1: W49
  Exam 2: TBD
  Exam 3: TBD

  Student's schedule and workload

  Contact teaching / lectures 7*1h (7h)
  Contact teaching / lab work 14*3h (42h)
  
  Self studying / independent work (85h)
  Exam (1h)
  
  Total: 135h

  Content scheduling

  VHDL/FPGA development
  Course duration 9/2022 - 12/2022
  Topics:
  - VHDL
  - combinatorial logic
  - sequential logic
  - state machines
  - FPGA
  After completing the course the student:
  - can design and implement digital logic using VHDL language
  - knows principles of FPGA technology and related tools
  - understands the basics of computer architecture

  Assessment criteria

  Failed (0)

  Less than 66% of lab exercises completed
  OR
  Less than 10 points in exam
  OR (TBD)
  Project work not submitted

  Assessment criteria – satisfactory (1-2)

  grade 1: 66% of lab exercises completed, 50% of max points in exam

  Assessment criteria – good (3-4)

  To be defined

  Assessment criteria – excellent (5)

  To be defined